Generally, a semiconductor chip package alone cannot receive electricity from outside to transmit or receive an electric signal, such that it is necessary to package a semiconductor chip to allow the semiconductor chip to receive the electric signal from and transmit the electric signal to the outside.
Recently, as the semiconductor chip package is manufactured in various configurations using various members such as lead frames, printed circuit boards and circuit films in consideration of reduced size of chip, heat emitting capacity and improved electrically performing capacity, improved reliability and manufacturing cost.
Furthermore, it is necessary to increase the number of input/output terminals (electrical leads) between the semiconductor chip and outside circuit substrate in response to super-integration of semiconductor chips. To this end, a semiconductor chip package of multi-row lead frame mounted with leads having 2 or more rows that separately connect the chip with outside circuit is receiving attention and interest.
FIG. 1 is a conceptual diagram illustrating a process of manufacturing a semi-conductor device according to the conventional manufacturing method of semi-conductor devices.
Referring to FIG. 1 (a), a predetermined thickness of lead frame material (23) consisting of copper, copper alloy or steel alloy is prepared. The surface of the lead frame material is coated using a first and second resist film (24, 25) in FIG. 1 (b), and photolithography treatment and development treatment are performed on the first and second resist films (24, 25) in FIG. 1 (c). The surface side of the lead frame material (23) is formed with junction terminals (14, 14a) of bonding wire (15) from the semi-conductor device (13) and an external wiring pattern (26) that has exposed a lead (17) portion bonded to the junction terminals (14, 14a). Furthermore, a rear side of the lead frame material (23) is formed with a rear wiring pattern (27) that has exposed a portion that becomes a terminal pad (11).
Referring to FIG. 1 (d), a noble metal plating (21. etching-resistant plating treatment) is performed on the surface exposed portion of the lead frame material (23) formed with the external and rear wiring patterns (26, 27) according to the first and second resist films (24, 25). The noble metal platings (20, 21) are not solved in the etching solution that is used in the subsequent processes and act as etching-resistant plating film.
Now, referring to FIG. 1 (e), the second resist film (25) at the rear side is removed, and in FIG. 1 (f), a half etching is performed on a rear side of the lead frame material (23) where the noble metal platings (20, 21) act as etching-resistant resist film. At this time, the surface side of the lead frame material (23) is covered with the noble metal plating (20) and the first resist film (24) to half-etch only the exposed portion of the internal wiring pattern (27) formed by the second resist film (25) and to form a concave portion (29).
It is sufficient to allow the depth of the half etching being at 4/5 to 1/2 of the thickness of the lead frame material (23). Thereby, a portion that becomes a terminal pad (11) arranged on a grid alignment becomes protruded.
Now, referring to FIG. 1 (f), the first resist film (24) at the surface side is removed. In FIG. 1 (h), resin (19) is injected into the half-etched concave portion (29) at the rear side using a mold device. In using the mold device, there is a gap between the mold and a surface with the noble metal plating (21) that becomes the terminal pad (11), and the gap may dirty the surface of the terminal pad (11) due to resin. Therefore, the molding process should be so performed as to allow the gap to narrow to a minimum allowable level (e.g., less than 10 micrometer).
As a result, the each terminal pad (11) is connected to the resin (19). Furthermore, separation of the first resist film (24) at the surface side may be performed after the resin (19) is injected into the concave portion (29).
Now, referring to FIG. 1 (i), an etching treatment is performed on the surface of the lead frame material (23). At this time, the noble metal plating (20) on the surface of the lead frame material (23) acts as a etching-resistant resist film, such that each junction terminal (14) and the junction terminal (14a) that is bonded to each lead (17) are electrically separated in non-bonding state. The each separated junction terminal (14, 14a) and the lead (17) are connected to the resin (19) to form a lead frame base (12).
Now, referring to FIG. 1(j), a semiconductor device (13) is centrally mounted on the lead frame base (12) formed through the aforementioned processes, and a wire bonding process is performed in which each electrode pad (22) of the semiconductor device (13) and the junction terminals (14, 14a) are connected by a bonding wire (15).
Furthermore, the lead frame base (12), the semiconductor device (13) and the bonding wire (15) are packaged while the terminal pad (11) is exposed at a rear surface using a mold device (not shown), whereby the semiconductor device (10) is completed. At this time, the surface of the terminal pad (11) exposed at the rear surface thereof may be padded by noble metal plating or welding, where the resin (19) at the rear surface may be partially removed by using chemicals or laser beam to protrude the terminal pad (11).
Now, referring to FIG. 1 (k), separation of the semiconductor device (10) arranged in parallel on a grid is performed to complete each semiconductor device (10).
In case of the existing semiconductor package substrate, particularly a metal substrate having an excellent heat emitting effect and electrical characteristic, in order to realize a die pad formed with a circuit of multi-row I/O (input/output) pad of various designs and packaged with chips, a circuit is realized by a way in which a surface treatment plating (typically Ni/Au) for wire bonding or soldering is performed, and photoresist is removed through etching.
Thereafter, a semiconductor chips are packaged via wire bonding in the assembly process and an epoxy mold compound is used to process the molding, and finally, a metal carrier material at a lower substrate-bonded portion is removed by etching to thereby complete the semiconductor device, whereby a multi-row I/O pad of portion size is made for an excellent thermal relief and electrical characteristic.
However, the conventional technique suffers from a disadvantage in that the plating is progressed following resister formation on etching, such that the etching solution creeps into a lateral surface of the etched resister metal layer when a circuit is formed to generate an undercut, thereby making it difficult to realize a circuit of a desired dimension. Another disadvantage is that the realized circuit is structurally weak, whereby separation or omission is generated to reduce the yield.
FIG. 2 is a drawing illustrating an example of a typical failure that is generated when a semiconductor device is manufactured according to the method of FIG. 1, where reference numeral 31 of FIG. 2 (a) is a metal material, 32 is an exemplary etching resist of Ni/Au layer, and 33 is a lower structure weakened by undercut, and where reference numeral 34 of FIG. 2 (b) is a normal pad and 35 is a loss pad. As noted, due to generation of undercut (33) in FIG. 2 (a), a failure such as the loss pad (35) of FIG. 2 (b) lowers the yield and deteriorates reliability of a circuit.
Furthermore, in the conventional technologies, especially where a substrate is employed using a metal material having an excellent heat emitting effect and an electrical characteristic, a photosensitive resist is employed for realizing a die pad packaged with chips and a circuit formation having a multi-row pad of various designs, a surface treatment plating for wire bonding or soldering is performed, photoresist is removed and a circuit is manufactured via an etching, whereby an excellent thermal relief and electrical characteristic relative to the multi-row I/O pad of portion size is realized.
However, when a circuit is configured by forming a resist to the etching to proceed the plating, etching solution is crept into a lateral surface of the etching resist metal layer to generate an undercut, whereby it is difficult to form a circuit of a desired dimension. Furthermore, the formed circuit is structurally weak to reduce the yield due to separation or omission during a high pressure rinsing at the assembly process.
In general, a semiconductor package suffers from a disadvantage in that a semi-conductor chip itself cannot receive an electricity from outside to receive or transmit an electric signal, such that chips are needed to be packaged for allowing the semi-conductor chips to receive from outside or transmit to outside various electric signals. Recently, in consideration of higher degrees of dimensional shrinkage of chips, improved thermal emission capacity and electric performance capacity, improved reliability and manufacturing cost, the semiconductor chips are manufactured in various configurations using lead frames, printed circuit boards, and circuit film.
Concomitant with tendency toward a semiconductor chip having a micro-size and a high integration degree, there is a need of increasing the number of I/O terminals of electrical leads between the semiconductor chip and an external circuit substrate. To this end, a semiconductor package of multi-row leadless frame is focused that is mounted with leads having two or more rows separately connecting the semiconductor chips with external circuit.
FIG. 3 is a flowchart illustrating a method of manufacturing a multi-row leadless frame and a semiconductor package using the conventional strip cut etching product.
The method is performed in the following manner. First of all, an initial etching is performed per strip portion relative to sheet (ST01). Lamination on both sides is performed to form a circuit (ST02). Plating is performed (ST03), and separation is performed to manufacture a multi-row leadless frame (ST04).
Once the multi-row leadless frame is manufactured, cutting is performed per chip portion, epoxy molding is performed and then a semiconductor package is completed (S505).
FIG. 4 is a conceptual drawing illustrating a manufacturing process according to FIG. 3, where FIG. 4(a) illustrates a first etching by strip portion at a strip cutting portion (011) relative to a sheet (010), FIG. 4(b) illustrates lamination (012) of photo-sensitive material on the strip-formed sheet, and FIG. 4(c) illustrates exposure using a photomask (013) and plating being performed, where, the strip formed on the existing sheet and the strip pushed aside by the lamination are different in positions thereof when the photosensitive material is exposed by photomask, thereby failing to form a proper pattern. In other words, a misalignment as much as ‘W’ in FIG. 4(c) is generated as a pattern failure.
FIG. 5 (a) is a plain view illustrating a sheet cut in strip portion from FIG. 4 (a), FIG. 5 (b) is a drawing illustrating an example of an improper pattern alignment due to failure to fix the strips, where reference numeral 014 is a formed semiconductor package, 015 is a metal material and 016 is a plated layer formed on the metal material.
As shown in FIG. 5(b), it can be noted that the plated layer (016) formed on the metal material (015) is not centrally formed on the metal material (015), whereby the pattern alignment is formed in a upwardly biased state from the center of the metal material (015).
As apparent from the foregoing, the conventional multi-row leadless frame has a disadvantage in that pattern formation experiences a difficulty due to a Cu device forming the strips being not fixed, because cutting is made based on strip portion when pattern process is performed per sheet. That is, the strip portion of a pattern portion in FIG. 5 is not fixed to lead to an improper pattern alignment during mask exposure.